1 Challenges in Digital IC Design
Course Overview
2 CMOS Inverter I
MOS Device Model with Sub-micron Effects
VTC Parameters - DC Characteristics
Problem Set #1 Out
3 CMOS Inverter II
CMOS Propagation Delay
Parasitic Capacitance Estimation
Layout of an Inverter
Supply and Threshold Voltage Scaling
SPICE Simulation Techniques
Tutorial on Design Tools - Layout of a CMOS Gate, Extraction, SPICE, IRSIM
4 CMOS Inverter III
Components of Energy and Power
Switching, Short-Circuit and Leakage Components
SPICE Simulation Techniques
5 Combinational Logic I
Static CMOS Construction
Ratioed Logic
Problem Set #1 Due
Problem Set #2 Out
6 Combinational Logic II
Pass Transistor / Transmission Gate Logic
Introduction to Dynamic Logic
7 Combinational Logic III
Dynamic Logic Design Considerations
Power Dissipation in CMOS
8 Combinational Logic IV
Power Consumption in CMOS Logic (cont.)
Leakage Power Dissipation
Logical Effort Sizing - Performance Optimization of Digital Circuits
Problem Set #2 Due
Problem Set #3 Out
9 Arithmetic Structures / Bit Slice Design
Adders, Multipliers, Shifters
Design Methodology
Layout Techniques and Mapping

Project Schedule and Guidelines

10 Evening Session on Exploring Project Ideas
Finish Arithmetic Structures and Project Ideas
11 Guest Lecture by Prof. Tayo Akinwande
Integrated CMOS Processing
12 Sequential Circuits I
Classification / Parameters
Static Latches and Register
Problem Set #3 Due
Problem Set #4 Out
13 Sequential Circuits II
Race Condition
Dynamic Latches and Registers
Two Phase vs. Single Phase
1-Page Project Proposal Due
Quiz #1
Covers Inverter, Combinational Logic
14 Sequential Circuits III
Pulse Based Registers
Latch vs. Register Systems
15 Interconnect
Capacitance Estimation
Buffer Chains
Low Swing Drivers
Power Distribution
Problem Set #4 Due
Problem Set #5 Out
16 Interconnect (cont.)
Issues in Timing - Impact of Clock Skew and Jitter
17 Clock Distribution
Origins of Clock Skew / Jitter and Impact on Performance
Clock Distribution Techniques
Self-timed Circuits
18 Memory I: ROM / EPROM / PLA Design
Organization / Architecture
Cell Design
PLA Folding Techniques
Problem Set #5 Due
19 Memory II: SRAM Design
Cell Design
Differential Sense Amplifiers
20 Memory III
DRAM Design
Single Ended Sense Amplifier
CMOS Scaling
Quiz #2
Covers Arithmetic Structures, Inter-connect, Sequential Circuits and Memory
21 Advanced Voltage Scaling Techniques
DC-DC Converter Design
Performance Feedback
Dynamic Voltage / Frequency Scaling
22 Power Reduction Through Switching Activity Reduction

Testing in VLSI
Defects, Fault Models, Path Sensitization
Scan, Built-in-self Test, IDDQ
23 Presentation of Final Projects Project Report Due
24 Presentation of Final Projects (cont.)